Pre-Lab 4 1) 2) What is AOl and draw the gate level diagram for the same. Also give the expression. Write the Verilog code for the gate diagram A small example related to the pre-lab is given. Use that to complete the rest. Example code: module Block (input A, B, C, output Y); Endmodule Hint: Use wire assignment for the output signal from the logic gates. Example module Inverter (input A, output Q) Wire Q = ~A; endmodule