PROBLEM 1 (10 PTS) Leading Zero Detector: This iterative circuit processes a 15-bit input (MSB first) and generates the number of leading O's. before the first 1. Example: If the sequence is: 0000 0000 0111 010 R = 9 If the sequence is: 0001 0001 0011010 R = 3 Q-0. The figure depicts the (in ASM form) and a datapath circuit. Note: Counters. If E-sclr1, Input data: x (entered sequentially, MSB first). Output data: R. Complete the timing diagram of the digital circuit where one sequence is evaluated. X AR LEADING-O start - DETECTOR done reset 0 ER 1. scrR 1 EQ1, sciro1 eb 1, db0 done ERCE QUI4,R EQUE 04, ebsdresar db Z FSM start - SIRIscle > 2 counter O to 15 Counter EQ reset EQ0 to 15 scrodb-Dob ER eb-E sche 0 clock done 1 EQ1, scho1 ER 1. scirR1 start clock 722222222 2222 resetn start X14X13X12 X11 X10 XgXg; X X6 X5 X5 X3 X2X1 Xo XOXOXOXOXOXOXOX OX 1 X 1 X 0 X 1 X 1 X 1 XOXO done PROBLEM 1 (10 PTS) Leading Zero Detector: This iterative circuit processes a 15-bit input (MSB first) and generates the number of leading O's. before the first 1. Example: If the sequence is: 0000 0000 0111 010 R = 9 If the sequence is: 0001 0001 0011010 R = 3 Q-0. The figure depicts the (in ASM form) and a datapath circuit. Note: Counters. If E-sclr1, Input data: x (entered sequentially, MSB first). Output data: R. Complete the timing diagram of the digital circuit where one sequence is evaluated. X AR LEADING-O start - DETECTOR done reset 0 ER 1. scrR 1 EQ1, sciro1 eb 1, db0 done ERCE QUI4,R EQUE 04, ebsdresar db Z FSM start - SIRIscle > 2 counter O to 15 Counter EQ reset EQ0 to 15 scrodb-Dob ER eb-E sche 0 clock done 1 EQ1, scho1 ER 1. scirR1 start clock 722222222 2222 resetn start X14X13X12 X11 X10 XgXg; X X6 X5 X5 X3 X2X1 Xo XOXOXOXOXOXOXOX OX 1 X 1 X 0 X 1 X 1 X 1 XOXO done