Problem #1

Given the following sequence of assembly language instructions:

I1: lw $3, 100($5)

I2: add $6, $3, $2

I3: sub $9, $3, $8

I4: lw $1, 2000($9)

I5: add $5, $4, $3

I6: addi $7, $1, #8

(c) Now assume there is a data forwarding circuit and hazard detection unit in this pipelined processor and data is written in the first half-cycle and read in the second half-cycle. Show a pipeline execution diagram for the program, where all stalls are marked with ** and identify the inputs and outputs of the data hazard detection unit in cycles when stalls are inserted.