Problem 2: Using Verilog, design a Moore FSM that has a single input x and a single output z. The state machine has to generate z = 1 when the previous four values of x were 1001 or 1111; otherwise, z = 0. Overlapping input patterns are allowed. An example of the desired behavior is:

 x: 0 1 0 1 1 1 1 0 0 1 1 0 0 1 1 1 1 1 z: 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 1 

Hint: First draw a state diagram, then derive the state assignment table. Eight states are enough.