PROBLEM 2: VERILOG (4 POINTS) Write the Verilog module for a PWM module. The module takes in a number between 0 to 63 and a clock input. The output of the module is a signal that its duty cycle changes between 0 to 100% with 64 total resolutions steps (0% to 100%). Duty cycle is ratio of time that the output signal is one to the time period of the signal. Figure below shows the three different duty cycles. 43.75V 75% 25% 75% 25% 75% 25% ...2.5V 20% 20% 20% 20% 20% 30%