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Problem 3 ( 2 0 Points ) For this problem assume the pipelined RISC - V microarchitecture implementation that is shown in the slide titled:
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For this problem assume the pipelined RISCV microarchitecture implementation that is shown
in the slide titled: RISCV Pipelined Processor with Hazard Unit. That implementation has a
Hazard Unit that handles both data forwarding as well as stalling for load instruction data
hazard. Also assume a memory system that returns the result within one cycle.
a The pipelined RISCV processor is running the following code segment.
Using a diagram similar to the one in the slide "Stalling to solve Load Data Hazard",
show both the forwardings and stalls needed to execute the above six instructions on
the pipelined RISCV processor.
b Expressed as a number of cycles, what is the execution time of the program segment in
part a
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