PROBLEM 5 (17 PTS) . Complete the following timing diagram (A and P are specified as hexadecimals) of the following Iterative unsigned multiplier. The circuit includes an FSM (in ASM form) and a datapath circuit. Register (for P): sclr: synchronous clear. Here, if sclr = E = 1, the register contents are initialized to 0. . Parallel access shift registers (for A and B): If E = 1: s_l= 1 Load, s_l= 0 Shift DA - 4 4 0000 "0000"&DA resetno reset- S1 scirP EP 1 1 0din TI 1 V Shift-left Shift-right selre ELEP E-1 FSM done = 1 EP - sclrP sclr P done EP - clock narorooooo resetn TOT XIII I 1 110 i 1101 -- 1 1 | I - - - 00 I-- 1 1 1 -- -- JLJJL - 1 1111 1 1 1 -- -!!-LL- - - TTT II. IRIT - 1 - SI! -- - - 1 1 1 -TTTT - I-- - - scl rP EP done