Problems in this exercise assume that individual stages of the datapath have the following latencies:

IF 250 ps ID 300 ps EX 150 ps MEM 500 ps WB 200 ps

a)What is the clock cycle time in a pipelined processor?

b)What is the clock cycle time in a single cycle processor?

c)What is the total latency of a R-type instruction in a pipelined processor?

d)What is the total latency of a R-type instruction in a single cycle processor?