Provide a minimised version of a circuit that implements:

$f=A\frac{*}{b}ar(C)*(Bo+D)\frac{+}{b}ar((\frac{?}{\text{b}\text{a}\text{r}}(A))+B+(\frac{?}{\text{b}\text{a}\text{r}}(C))+D)+A\frac{*}{b}ar(B)*D\frac{+}{b}ar((\frac{?}{\text{b}\text{a}\text{r}}(B))+(\frac{?}{\text{b}\text{a}\text{r}}(D)))\frac{*}{b}ar(Ao+C)$

$($i$)$ using AND$/$OR gates $($which can have any number of inputs$)$ and NOT gates only;

$($ii$).$ using NAND gates only;

$($iii$)$ using an $3-8$ line decoder and any additional necessary logic;

$($iv$)$ using a $16-1$ line multiplexer and any additional necessary logic.