Q$1$: Consider a machine with a byte addressable main memory of $64$Kbyte with $8$byte Block size.

Assume that direct mapped cache consisting $32$ lines. Write answer of the following questions $[20$ Marks$]$

a$).$How $64$Kbyte Main memory address divided into tag, block$/$line number, and byte number

b$).$ Into what line would bytes with each of the following addresses be stored?

$0001000100011011$ :

$1100001100110100$ :

$1101000000011101$ :

$1011111101010001$:

FA$02$:

EC$4$F:

c$).$Suppose the byte with address $0001101000011010$ is stored in the cache. What

are the addresses of other bytes stored along with it$?$

d$).$How many total bytes of memory can be stored in the cache?

Q$2$: Assume a $4-$way set associative cache of size $32$KB$,$ each block having four $64-$

bit words. The system is based on $64-$bit physical address and uses byte addressing.

Find the total number of offsets, index and tag bits. $[20$ Marks$]$

$$ Main Memory Size :

$$ Tag Bits:

$$ Offset Bits:

$$ Index Bits:

Q$3$: Assume a direct$-$mapped cache of $64$Byte and data access sequence given below where the

memory and its contents are shown in the table on the right. Assume $4$byte addresses and a $4-$

byte data block. You are required to design a cache and calculate a Cache Hit and Miss $\%.$

Operations Address

Read $0$x$01$B$0$

Read $0$x$00$C$8$

Read $0$x$0214$

Read $0$x$0234$

Read $0$x$0160$

Read $0$x$0030$

Read $0$x$018$C

Read $0$x$0068$

Read $0$x$0062$

Read $0$x$01$A$4$

Read $0$x$01$CC

Read $0$x$01$A$3$

Read $0$x$0230$

Read $0$x$01$CC

Read $0$x$0212$

Hits: Hit Rate:

Miss: Miss Rate:

Q$4$: computer system has a two$-$level cache hierarchy consisting of a Level $1($L$1)$ cache and a Level $2$

$($L$2)$ cache. The system services memory requests with the following characteristics:

$$ L$1$ cache serves $3000$ memory requests, out of which $2550$ requests result in a cache hit.

$$ L$2$ cache serves $2800$ memory requests, out of which $2520$ requests result in a cache hit.

$$ L$1$ cache access time: $1$ nanosecond $($ns$)$

$$ L$2$ cache access time: $10$ ns

$$ Main memory access time $($miss penalty$)$: $100$ ns

Calculate the following:

$1.$ The percentage of memory accesses that result in a cache hit in the L$1$ cache.

$2.$ The percentage of memory accesses that result in a cache hit in the L$2$ cache.

$3.$ The number of memory accesses that result in a cache miss in both the L$1$ and L$2$ caches.

$4.$ The effective access time $($EAT$)$ for this cache hierarchy.