Q$2.$Design and implement a versatile FPGA$-$based system that utilizes foundational design components such as ILA, BRAM, timing constraints, attributes, and clock management. The project will be adaptable, allowing students to choose a specific application or functionality relevant to their professional field.

Requirements:

$1.$ System Concept:

$$ Students will conceptualize and design a system that could be used in their field of interest, such as data processing, control systems, communication interfaces, or any

other applicable area.

$$ The system should showcase the ability to manage complex operations, handle data efficiently, or improve system performance using FPGA capabilities.

$2.$ Block RAM $($BRAM$)$:

$$ Implement BRAM to manage data storage efficiently within the FPGA, suitable for the chosen application.

$$ Discuss how BRAM is utilized to optimize system performance and data handling.

$3.$ Timing Constraints:

$$ Apply specific timing constraints to ensure reliable and efficient system performance.

$$ Include constraints that manage setup times, hold times, and clock domain

crossings, tailored to the designed system.

$4.$ Attributes:

$$ Use synthesis attributes to guide the FPGA compiler in resource allocation and

optimization, such as $`$KEEP$`,`$DONT$\_$TOUCH$`,$ and others appropriate for the

design.

$5.$ Clocking Wizard:

$$ Design the system with multiple clock domains if necessary, using the clocking

wizard to generate and manage these clocks.

$$ Explain the rationale behind clock selection and strategies for mitigating issues

related to multiple clock domains

$6.$ Integrated Logic Analyzer $($ILA$)$:

$$ Integrate ILA cores to facilitate real$-$time debugging and monitoring of the system.

$$ Set up appropriate triggers and capture conditions to diagnose issues or verify

system operations during development.

Deliverables:

$-$ Conceptual design document describing the system and its relevance to the chosen field.

$-$ Complete Verilog$/$VHDL code implementing the system.

$-$ Simulation results and synthesis report detailing performance metrics and resource

utilization.

$-$ A comprehensive final report documenting the design rationale, challenges, and

implementation details, signed and commented upon by your mentor.

$-$ A presentation or demonstration that illustrates the system's functionality and real$-$world applicability

Deliverables: $-$ Conceptual design document describing the system and its relevance to the chosen field. $-$ Complete Verilog$/$VHDL code implementing the system. $-$ Simulation results and synthesis report detailing performance metrics and resource

utilization. $-$ A comprehensive final report documenting the design rationale, challenges, and implementation details,, signed and commented upon by your mentor. $-$ A presentation or demonstration that illustrates the system's functionality and real$-$world applicability.