Q$3.$ The instruction cycle of a CPU has the following $5$ states $($cycles$)$:

$1.$Instruction fetch: $60ns,2.$Instruction Decode: $30ns,3.$Operand fetch: $40ns,4.$Execution: $30ns,5.$Interrupt: $200ns.$

Assume that the CPU accesses the memory in the instruction fetch and operand fetch cycles but not in the decode and execution cycles.

In this system there is a $2-$wire $(BR,BG$ DMAC that is configured to transfer $10$ words from the I$/$O interface to the memory using the Cycle$-$Stealing technique. The DMAC type is flyby $($implicit$).$ But, after completing the transfer of $5^{th}$ word, DMAC changes its transfer mode to Burst Mode instead of Cycle$-$Stealing.

The memory access time and I$/$O interface access times are both $60ns.$

Assume that we start a clock $($Clock $=0)$ when the CPU begins to run a program that consists of $10$ instructions.

When the CPU is in the instruction fetch cycle for the first instruction $($Clock $=5ns),$ the DMAC attempts to start the data transfer.

a$.$ When $($Clock $=?)$ will the DMAC complete the transfer of the first word? Why?

b$.$ When $($Clock $=?)$ will the CPU finish the first instruction? Why?

c$.$ When $($Clock $=?)$ will the DMAC complete the transfer of all $10$ words? When will the CPU complete the run of the entire program with $10$ instructions?

$(40$P$)$