Q$4)$ Consider the following sequence of instructions, and assume that it is executed on a $5-$stage pip

data path $($IF$,\frac{D}{R},$ALU,$DM,$ WB$.$ Also assume that writing into a register happens in the first half of the

clock cycle while reading from a register happens in the second half of the clock cycle. Also, assume tha

the hardware will apply "predicted$-$ taken" predictor $($i$.$e$.$ always predict taken$)$ to fetch the instructio

after the branch and flush it later in case of misprediction. Also, assume branch takes two cycles as w

did in class.

$($a$)$ List the read$-$after$-$write data dependencies. As an example, $x$ on $y($$$t5)$ shows instruction $x$ has d

dependency on instruction y since it is reading register $$t5.$

$($b$)$ Assume the $5-$stage MIPS pipeline with no forwarding, what is the total number of stall cycles? W

is the execution time $($in cycles$)$ for the whole program? Show your work.

$($c$)$ Assume the $5-$stage MIPS pipeline with full forwarding, what is the total number of stall cycles?

is the execution time $($in cycles$)$ for the whole program? Show your work.