Q$6.$ Caches are important to providing a high$-$performance memory hierarchy to processors. Below is a list of $64-$bit memory address references, given as word addresses.

$003,0b4,02b,002,0xbf,058,0be,00e,0xb5,$

$0$x$2$c$,$ Oxba, $0$xid

a$)$ For each of these refenences, identify the binary word address, the tag, and the index given a direct$-$mapped cache with $16$ oneword blocks. Also list whether each reference is a hit or a miss, assuming the cache is initially empty.

b$)$ For each of these references, identify the binary word address, the tag, the index, and the offset given a direct$-$mapped cache with two$-$word blocks and a total size of eight blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty.

Q$7$: By convention, a cache is named according to the amount of data it contains $($i e$,$ a $4KB$ cache can hold $4KB$ of data$)$; however, caches also require SRAM to store metadata such as tags and valid bits. For this exercise, you will examine how a cache's configuration affects the total amount of SRAM needed to implement it as well as the performance of the cache. For all parts, assume that the caches are byte addressable, and that addresses and words are $64$ bits.

A$)$ Calculate the total number of bits required to implement a $32$ KBB cache with two$-$word blocks.

B$)$ Calculate the total number of bits required to implement a $64KJB$ cache with $16-$word blocks. How much bigger is this cache than the $32$KIB cache described in Exercise Q$7.$ A$?($Notice that, by changing the block size, we doubled the amount of data without doubling the total size of the cache.$)$

Q$8$: For a direct$-$mapped cache design with a $64-$bit address, the following bits of the address are used to access the cache.

$\backslash$table$[[$Tas$,$Indox,Offset$],[63-10,9-5,4-0$