Q: For a four-way set associative cache design with a 32-bit address, the following bits of the address are used to access the cache.

Tag: Bit 9 to Bit 31, Index: Bit 3 to Bit 8, Offset Bit 0 to Bit 2

1. What is the cache block size in words? Show calculation.
2. What is the size of the cache?
3. What is the ratio between total bits required for such a cache implementation over the data storage bits? Show all calculations.
4. After power on, how many blocks are replaced if the following byte-addressed cache references are recorded:

0, 4, 16, 132, 232, 160, 1024, 30, 140, 3100, 180, 2180