Q1. Clock skew 1. Given the circuit in figure 1, each 2-input or gate has a propagation delay of 60 ps and a contamination delay of 40 ps. Each flip-flop has a setup time of 30 ps, a hold time of 20 ps, a clock-to-Q propagation delay of 80 ps, and a clock-to-Q contamination delay of 40ps. DQ ADLADA FF1 FF4 D Q FF5 to to clk FF6 GDQ FF2 Do FF7 to a FF3 FF3 clk b. I a. Find the critical path of the circuit If there is no clock skew, What is the maximum frequency of the circuit? C. Is there any hold time violation in the circuit? If there is not, how much clock skew can the circuit tolerate? If there is, how would you fix the circuit? Q1. Clock skew 1. Given the circuit in figure 1, each 2-input or gate has a propagation delay of 60 ps and a contamination delay of 40 ps. Each flip-flop has a setup time of 30 ps, a hold time of 20 ps, a clock-to-Q propagation delay of 80 ps, and a clock-to-Q contamination delay of 40ps. DQ ADLADA FF1 FF4 D Q FF5 to to clk FF6 GDQ FF2 Do FF7 to a FF3 FF3 clk b. I a. Find the critical path of the circuit If there is no clock skew, What is the maximum frequency of the circuit? C. Is there any hold time violation in the circuit? If there is not, how much clock skew can the circuit tolerate? If there is, how would you fix the circuit