Q1. Latches For the following latch, fill out the truth table showing the characteristic equation of the circuit. Q(t+A) Q(t) 0 O 0 0 1 1 0 1 / 101 1 1 0 Q2. Timing Complete the following timing diagram. Assume flip flops are rising edge triggered. Each flip-flop has a synchronous reset. You may assume that the delay of gates is infinitesimally small so it can be considered to be zero. Clock Reset OOONO