Q1) The following two entity declarations contain two of the most common syntax errors made in VHDL. What are they? a) entity ckt_a is port 1 J,K : in std_logic; CLK : in std_logic end ckt_a; 0 : out std_logici b) entity ckt_b is port ( mr_fluffy : in std_logic_vector(15 downto 0 ); mux_ctr1 : in std_logic_vector (3 downto 0); byte_out : out std_logic_vector ( 3 downto 0); end ckt_b