Q10. The von Neumann architecture is based on which concept? A. data and instructions are stored in a single read-write memery B. the contents of this memory are addressable by location C. execution occurs in a sequential fashion D. all of the above is called A software Q12: The processing required for a single instruction is called a(n) A execute D. a register cycle - 8. fetch C instruction D. packet is generated by a failure such as power failure or memory parity error. A. VO interrupt C. timer interrupt B. hardware failure interrupt D. program interrupt is generated by some condition that occurs as a result of an instruction Q14. A(n) execution A. timer interrupt c. program interrupt B. Vo interrupt D, hardware failure interrupt Q15. The interconnection structure must support which transfer? memory to processor processor to memory VO to or from memory all of the above A. B. C. D. Q16. A bus that connects major computer components (processor, memory,VO) is called A system bus C. data bus D. control bus B. address bus Q17. The A. system lines are used to designate the source or destination of the data on the data bus. B. data lines D. address lines C. control lines Q18. The data lines provide a path for moving data among system modules and are collectively called the C. data bus D. system bus B. address bus Mean is a good candidate for comparing the execution time performance of B. Arithmetic A. control bus Q19: A(n)- several systems A. Composite D. Evaluation C. Harmonic law deals with the potential speedup of a program using multiple processors Q20: D. Murphy's compared to a single processor A. Moore's C. Little's B. Amdahl's -and provides the Q21: The use of multiple processors on the same chip is referred to as potential to increase performance without increasing the clock rate D. MPC C. data channels B. GPU A. multicore A2