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Q2 [5 points]: Suppose the hypothetical processor of Figure 1.3 also has two I/O instructions: 0011=LoadACfrom1/0 0100=SUBfromAC In these cases, the 12-bit address identifies a
Q2 [5 points]: Suppose the hypothetical processor of Figure 1.3 also has two I/O instructions: 0011=LoadACfrom1/0 0100=SUBfromAC In these cases, the 12-bit address identifies a particular external device. Show the program execution (using the format of Figure 1.4) for the following program: 1. Load AC from device 7. 2. SUB from AC contents of memory location 880 . 3. Store AC to memory location 881. Assume that the next value retrieved from device 7 is 6 and that location 880 contains a value of 5 . Program counter (PC)= Address of instruction Instruction register (IR)= Instruction being executed Accumulator (AC)= Temporary storage (c) Internal CPU registers 0001= Load AC from memory 0010= Store AC to memory 0101= Add to AC from memory (d) Partial list of opcodes Figure 1.3 Characteristics of a Hypothetical Machine Fetch stage Execute stage Figure 1.4 Example of Program Execution (contents of memorv and registers in hexadecimal)
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