Q2. Moore/Mealy

A sequential network has one binary input x(t) and one binary output y(t). The network produces y = 1, whenever input pattern x(t 1, t)= 10 or 11. Otherwise, the output y = 0.

a) Design a Mealy FSM for the network.

b) Draw the state table.

c) Implement the corresponding sequential circuit using a minimum number of gates and flip-flops.

Note: make sure to answer part a,b, and C pls