Q2: VHDL allows designers to describe circuits at behavior level. The advantage is so the designers do not need to actual go through the process of Boolean optimization. This can be scen from the followings. L. Use Quartus to realize the following descriptions and then use the RTL. viewer to see the circuits. Provide the RTT. Views of the circuits. Are they identical? II. Fill in the truth table below according to the above descriptions: III. Derived the Boolean equation of version #1 above in sum-of-product or product-of-sum form; and also draw a logic diagram using AND, OR and NOT (inverter) gates. Write a VHDL assignment statement (using AND, OR, NOT, etc. logic operators from std_logic package) to realize this Boolean equation. You may compile the VHDL code and use RTL viewer to generate a logic diagram for comparison (optional)