Q2:1 designed a static CMOS ASIC that runs at 400 MHz and IV supply voltage, and it consumes 20 mW. I later redesigned it to run at 300 MHz and 1.8V supply voltage using a cheaper chip fabrication technology. The new design has 120% of the die size of the original design, and its toggle rate of nodes is half the original design. How much power does the new design consume? Q2:1 designed a static CMOS ASIC that runs at 400 MHz and IV supply voltage, and it consumes 20 mW. I later redesigned it to run at 300 MHz and 1.8V supply voltage using a cheaper chip fabrication technology. The new design has 120% of the die size of the original design, and its toggle rate of nodes is half the original design. How much power does the new design consume