Q3: Assume multiple cycle MIPS: Assume that x and y are arrays of words and the base address of x is in R1 and the base address of y is in R2. If ALU instructions (add and addi) take 1 cycle to execute, load/store (Iw and sw) take 5 cycles to execute, and the branch (bne) instruction takes 3 cycles to execute; a. How many instructions are executed during the running of the following code? b. How many cycles are needed to execute the code (all iterations)? c. Calculate the average CPI (cycles per instruction)? d. Calculate the Branch Target Address (loop) when branch is taken? e. Identify the Read after Write (RAW) hazards that exist among the Loop instructions (only)? f. What are the five pipeline stages of a MIPS machine (see table below as a hint)? Write one sentence explaining each stage. g. Use the table below to fill out the processing of the above code through the pipeline machine. Assume all instruction now take the same number of cycles to execute, and branch is never taken. Clock Cycles h. How many clock cycles it take to process the first 11 instructions using the pipeline machine above? i. If the LW instruction causes 2 stall cycles, and the LW is 30% of the code, and that Branch causes 3 stall cycles and it is 10% of the code. Calculate the CPI for the noneideal pipeline? Ideal pipeline CPI is equal to 1