Q.4 (30 Points) Assume that, in MIPS assembly, the base address of an integer array A is stored in $a0. a) (6 points) Fill in the blanks with the MIPS instructions corresponding to the following C code (Do not use any branch instruction): A[0]=A[0]+1A[1]=A[1]+1 b) Assume that the code in (a), is executed on a 5-stage pipelined MIPS processor (with the stages IF, ID, EX, MEM and WB). By considering the instructions between 2-7, which are inserted in (a) by yourself, draw the pipeline charts for the following cases. (Whenever a stage gets stalled, fill that stage with an "S". It is allowed to write and read a register at the same cycle. If data forwarding is allowed, show the forwarding.) Make sure that you show the stages clearly as the following chart. b.1) (7 points) Assume that data forwarding is not allowed. b.2) (7 points) Assume that data forwarding is allowed. c) ( 10 points) If there is a stall in the case (b.2), reorder the instructions so that there will be no stalls. Draw the pipeline chart for the new order by showing the stages and forwarding (if necessary) clearly