Q4) Consider the following sequence of instructions, and assume that is is executed on a 5 -stage pipelined data path (IF, O/R, ALU, OM, WB. Also assume that writing into a register happens in the first half of the clockcourin....... ng from a register happens in the second half of the clock crcle: List the read-after-write data dependencies. As an example, x on y($+5) shows instruction x has data dependency on instruction y since it is reading register $15. Assume the 5-stage MiPS pipeline with no forwarding, what is the total number of stall cycles? What is the execution time (in cycles) for the whole program? Show your work. Assume the 5-stage MIPS pipeline with full forwarding, what is the total number of stall cycles? What is the execution time (in cycles) for the whole program? Show your work