Q4- Design a Finite State Machine (FSM) (a.k.a transducer) for each of the followings. For all of them consider that the end of inputs is marked with blanks (Bs). a) A transducer that receives two binary strings as inputs and output the result of the subtraction of the second one from the first one. You can assume that the input is read from right to left (The least significant digit to the most significant digit), and the first number is always greater than or equal to the second number. Note that the two strings might not have the same length. b) A Finite State Machine (FSM) that receives a number in octal (Base 8) and converts it to a number in binary. 7712111111001010 c) A transducer that converts a binary string to an octal number, you can assume that the input is read from right to left. Note that the length of the binary string might not be divisible by 3 . 1100=>14 d) A transducer that sends the input to the output with two delays. aabb=>aabb (Hyphens represent delays here but you know how to produce them in a transducer)