Q4 Design a fully dedicated architecture (FDA) of the following computational block: The equation is to be iterated for 500 times. Assume that x, y and z are 8-bit in size. (x + y)2 2x + y (e) Draw the FBD of the datapath unit (DU) and write the Verilog code for the DU. Z= Q4 Design a fully dedicated architecture (FDA) of the following computational block: The equation is to be iterated for 500 times. Assume that x, y and z are 8-bit in size. (x + y)2 2x + y (e) Draw the FBD of the datapath unit (DU) and write the Verilog code for the DU. Z=