qa Applied University

If $35x$ speedup is achieved from $96$ processors. What fraction of the original program can be sequential?

A

B$.2\mathrm{.}68\%$

C$.4\mathrm{.}34\%$

D$.$ None of the above.

An application runs on a $16-$processor MP that has a $158$ ns time to handle a reference to remote memory. Assume that all references $($except those involving communication$)$ hit the cache. The processor clock rate is $2\mathrm{.}1GHz$ and $\frac{C}{P}$I $($Cycle per instruction$)$ is $0\mathrm{.}7$ if all instructions hit the local cache. How much faster is the MP if there is communication compared to the case in which $0\mathrm{.}52\%$ of the instructions involve a remote reference?

A$.3\mathrm{.}318$

B$.3\mathrm{.}465$

C$.2\mathrm{.}425$

D$.$ None of the above.

Which of the following is correct about directory$-$based cache coherence protocols?

A$.$ Sharing status of each cache block kept in one location.

B$.$ It is challenging for Distributed Shared Memory $($DSM$).$

C$.(A+B.$

D$.$ Each core tracks sharing status of each block.

Cache coherence defines the behavior of reads and writes to the same memory location, While cache consistency defines the behavior of reads and writes with respect to accesses to other memory locations.

A$.$ True.

B$.$ False.

In the case of the MIPS single$-$cycle datapath and given the functional unit latencies a: shown in the table below. Answer questions $11$ to $12$

$\backslash$table$[[$Func$.$ Unit,Latency$],[$Memory read,$6$ ns$],[$Memory write,$10ns$