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Question 01 (CLO 1-5 pts) A function F (A, B, C) is implemented using the below circuit that consists of one 2-to-4 decoder, two
Question 01 (CLO 1-5 pts) A function F (A, B, C) is implemented using the below circuit that consists of one 2-to-4 decoder, two 4- to-1 muxes, and a NOR gate. Analyze the circuit to answer the questions below. B C 10 2:4 Decoder D1 D2 D3 1 A A A A 0 0 0 0 1 1 10 4:1 11 Mux 12 1 1 0 1 1 0 0 Y1 1 1 S1 SO a) (4 Points) Fill the truth table that shows the output of every component/gate. B Y1 Y2 F 0 0 A' A 1 C 0 1 0 1 0 O-OT 1 0 10 4:1 11 Mux 1 12 13 S1 SO Y2
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Digital Systems Design Using Verilog
Authors: Charles Roth, Lizy K. John, Byeong Kil Lee
1st edition
1285051076, 978-1285051079
