Question 1: [10 points]

Assume we have a 64-bit processor that can execute up to 44 instruction. Answer the following questions:

1. [5 Points] Show the design of fully associative L1 cache with 2¹² rows. Show the size of each segment of L1 cache.

2. [5 Points] Show the design of direct mapped cache with 2¹⁶ rows. Show the size of each segment of L2 cache.