Question #1: (40p) We have a 8-lines of L1 data cache. Let us assume each line has 256 bits and memory addresses have 16 bits of width, with byte-addressable memory. Indexing the cache is implemented by lowest-order bits. a) Determine the number of tag, index and offset bits. (5pt) b) Which types of bits does the cache tags contain? (5pt) c) What is the total number of bits necessary to apply the level 1 data cache? (5pt) d) Let us assume the processor accesses data addresses below when cache is initially empty. Show the hits and misses in the level 1 data cache (5pt). Ox0039: 0000 0000 0011 1001 Ox103B: 0001 0000 0011 1011 Ox954C: 1001 0101 0100 1100 OxFFF5: 1111 1111 1111 0101 OxBEEF: 1011 1110 1110 1111 Ox4360: 0100 0011 0110 0000 Ox02DF: 0000 0010 1101 1111 Ox8065: 1000 0000 0110 0101 Ox9528: 1001 0101 0100 1000 e) Let us assume that the level 1 data cache has a hit rate of 30% on your application, an access time of a single cycle, and a miss penalty to memory will be of 30 cycles. What will the AMAT time? (10pt) f) We want to increase the performance and we add a L2 cache to the system, what should the access time of the L2 cache with a hit rate of 50% in order to reduce the AMAT? (10pt)