QUESTION 1 : C Consider the following synchronous circuit, which consists of four registers and two logic gates (OR, XOR). The timing parameters of all logic elements are collected in the tables below. (A) Determine the minimum clock period (Tman) of the circuit. Malke sure to explain the methodology and steps you use in order to calculate this value. (B) Determine whether the circuit exhibits any hold-time violation. Mabe sure to explain the reasoning behind your answer. In case the circuit does exhibit a hold-time violation, explain how to fix it. (C) Assume that during manufacturing of this circuit, it is not possible to guarantee that the dock signal arrives simultaneously to all registers. Instead, due to some imperfections in the clock distribution line, the clock signal arrives with a delay of =1ns to REG 4 , with respect to all other reyisters. In other words: the clock edges arrive =1 ns later to REG 4. This imperfection is captured in the circuit below. Analyze this situation carefully and describe, both qualitatively and quantitatively, how this delay affects the minimum clock period Tmin found in part. (A) and the presence of hold-time violations in part (B)