Question 1. Chocolate Vending Machine You are to design the control for an automatic chocolate vending machine to the following specification: The chocolates inside the machine cost $25 and the vending machine accepts bank notes of $5, $10, and $25 only. The inputs to the control are a set of three signals that indicate what kind of note has been deposited, as well as a reset signal. The control should generate an output signal that causes the chocolate to be delivered whenever the amount of money received is $25 or more (no change is given). Once the chocolate has been delivered, some external circuitry will generate a reset signal to put the control back into its initial state. Transform the word description into a finite-state machine (FSM). Decide which features are implemented by the FSM and which features by combinational logic. 1. Draw a state diagram and list the state table for the FSM. 2. Implement the FSM using D, T and JK flip-flops. 3. Verify the D flip-flop implementation in (2). 4. Write Verilog HDL models for the machine based on the state diagram and the D flip-flop sequential circuit that you implement. Make sure you have adequate and clear comments in your code. Write a test bench to verify the operation of the FSM. The test bench should consider all different scenarios. Simulate the behaviour of the FSM using the test bench you developed. *Refer to assignment II marking guidelines for detailed breakdown Question 1. Chocolate Vending Machine You are to design the control for an automatic chocolate vending machine to the following specification: The chocolates inside the machine cost $25 and the vending machine accepts bank notes of $5, $10, and $25 only. The inputs to the control are a set of three signals that indicate what kind of note has been deposited, as well as a reset signal. The control should generate an output signal that causes the chocolate to be delivered whenever the amount of money received is $25 or more (no change is given). Once the chocolate has been delivered, some external circuitry will generate a reset signal to put the control back into its initial state. Transform the word description into a finite-state machine (FSM). Decide which features are implemented by the FSM and which features by combinational logic. 1. Draw a state diagram and list the state table for the FSM. 2. Implement the FSM using D, T and JK flip-flops. 3. Verify the D flip-flop implementation in (2). 4. Write Verilog HDL models for the machine based on the state diagram and the D flip-flop sequential circuit that you implement. Make sure you have adequate and clear comments in your code. Write a test bench to verify the operation of the FSM. The test bench should consider all different scenarios. Simulate the behaviour of the FSM using the test bench you developed. *Refer to assignment II marking guidelines for detailed breakdown
