Question $1$

Suppose a byte$-$addressable memory has a $2M-$addressable space and cache consists of $8K$ blocks, where

each block contains $8$ bytes.

Q$1-1.$ In the direct mapping function, divide the bits into tag, line, and offset.

Answer: tag$=,$ block $=,$ offset $=$

Q$1-2.$ In the directed mapping, give the tag and line number of the address $$1BC_7,$ in hexadecimal.

Tag $=,$ Block $=,$ Offset $=$

Q$1-3.$ In $4-$way set associative mapping function, divide the bits into tag, set, and offset.

Answer: tag$=,$ set $=,$ offset $=$

Q$1-4.$ In a $4-$way set associative mapping function, give the tag and set number of the

address $$1$B$96$C$7,$ in hexadecimal.

Tab$=,$ Set $=,$ Offset $=$

Question $2$

A certain RISC processor has an on$-$chip cache with the following specifications:

$32-$bit wide address and data busses

On$-$chip instruction cache

cache is $64K$ bytes, organized as a $4-$way set associative

Cache line $($block$)$ size $=32$ bytes

$100MHz$ clock frequency

Average cache hit rate $=98\%$

Instructions located in cache execute in $1$ clock cycle

Instructions that are not found in the on$-$chip cache will cause the processor to stop all program execution

and do a burst memory read access of one refill line from main memory to the cache.

For this memory design, burst accesses from main memory requires an address set$-$up time of $5$ clock

cycles, and then all subsequent burst fetches from main memory require $2$ clock cycles per memory fetch,

$($i$.$e$.,32$ bits or $4$ bytes per each memory fetch$).$

What is the effective instruction execution time for this RISC processor?

EET$=$ ns