Question 3 (7 4+8-19 points) a. A k-way set associative cache consists of 128 lines divided into four-line sets 64K blocks of 16 bytes each i. What is k? (1 point) i. What is the format of main memory address? (4 points) ii What is the size of the cache in bytes? (2 points) b. For the same size cache and block size as part (a), what would be the format of main memory address if direct cache is to be designed " s. Design a 32-bit memory of total capacity 32768, bits using SRAM chips of size 64x4. Give the aray configuration of the chips on the memory board showing all input and output signals for assigning this memory to the lowest address. The design should allow byte, word and double word accesses 3226 figure liu o problem 2(b) for 2-way set associative case. Using ine if there is a hit (5+9-14 points) the following or miss. In case of a hit, read the data from the cache. (ii) ECIOB (iv) AC00A (u) 58006 Tag 110011 44 155 09 67 FE 1 22 33010110 S99 AA 0 1122 33 44 55 16677 7809 67 FE 87 90 76 EF ) glot 0o 000 11 b. Design a 32-bit memory of total capacity 16384 bits using SRAM chips of size 128x2. Give the array configuration of the chips on the memory board sh memory to the lowest address. The design assigning this word and double word accesses 6384 6c autput