Question 4. Produce the complete design for the accumulator system below. You are designing a system to accumulate 8-bit unsigned integer data. The system is to have an active- low synchronous reset. The system shall set the 64-bit output, acc, to zero and wait until the input start asserts before accumulating anything. The input, d_in, should be accumulated in each clock period following the assertion of start. The accumulation continues until the input done is asserted. Following done, the output acc shall retain the accumulated value until a new accumulation begins with another assertion of start. Note the following 1) The system does not accumulate the value on d.in when start asserts. Begin accumulating with the value in the next clock period 2) The system does accumulate the value on d.in when done asserts. 3) The process may repeat any number of times. Each time, the accumulation should start from zero. A timing diagram showing a complete accumulation followed by the start of another is shown in Figure 2. 4.1. Top LEVEL BLOCK DIAGRAM Draw the top level block diagram for the design. 4.2. SECOND LEVEL BLOCK DIAGRAM Draw the second level block diagram for the design. Note that you may not know the signals between the datapath and controller. Simply leave them out for now. You need only to allocate the top level signals to the datapath and controller. Question 4. Produce the complete design for the accumulator system below. You are designing a system to accumulate 8-bit unsigned integer data. The system is to have an active- low synchronous reset. The system shall set the 64-bit output, acc, to zero and wait until the input start asserts before accumulating anything. The input, d_in, should be accumulated in each clock period following the assertion of start. The accumulation continues until the input done is asserted. Following done, the output acc shall retain the accumulated value until a new accumulation begins with another assertion of start. Note the following 1) The system does not accumulate the value on d.in when start asserts. Begin accumulating with the value in the next clock period 2) The system does accumulate the value on d.in when done asserts. 3) The process may repeat any number of times. Each time, the accumulation should start from zero. A timing diagram showing a complete accumulation followed by the start of another is shown in Figure 2. 4.1. Top LEVEL BLOCK DIAGRAM Draw the top level block diagram for the design. 4.2. SECOND LEVEL BLOCK DIAGRAM Draw the second level block diagram for the design. Note that you may not know the signals between the datapath and controller. Simply leave them out for now. You need only to allocate the top level signals to the datapath and controller