Question: Design $8-$bit Serial Adder with Accumulator using components of full adder, D$-$FF$,$ serial adder control circuit, and $8-$bit shift register. The $8-$bit shift register has serial in$,$ shift right, load, and clock as one$-$bit inputs, d as $8-$bit input, and q as $8-$bit output. The main design has load, start, clock as one$-$bit inputs, a & b as $8-$bit inout.

Please upload the VHDL code as text,

screen shots of RTL viewer & Technology map viewer, and simulation results using quar $\_$tus $($Quar$\_$tus Pri~me $)$ if you can.

Use these codes below to solve the question. Please do not use AI tools to write the code

$($shift$\_$reg$\_4$b$.$vhd$)$:

library ieee;

use ieee.std$\_$logic$\_1164.$all;

use ieee.std$\_$logic$\_$signed.all;

entity shift$\_$reg$\_4$b is

port $($d: in bit$\_$vector $(3$ downto $0)$;

sh$,$ ld$,$ sin$,$ clk: in bit;

q: out bit$\_$vector $(3$ downto $0))$;

end shift$\_$reg$\_4$b;

architecture shift$\_$reg$\_4$b of shift$\_$reg$\_4$b is

signal qint: bit$\_$vector $(3$ downto $0)$;

begin

process $($clk$)$

begin

if $($clk$\text{'}$event and clk$=\text{'}1\text{'})$ then

if ld$=\text{'}1\text{'}$ then

qintd;

elsif sh$=\text{'}1\text{'}$ then

qint sin&qint$(3$ downto $1)$;

end if;

end if;

end process;

q qint;

end shift$\_$reg$\_4$b;

$----------------------------------------$

$($dff$.$vhd$)$ :

entity dff is

port $($rst$,$ clk$,$ d: in bit;

q: out bit$)$;

end dff;

architecture dff of dff is

signal q$\_$int: bit;

begin

process $($rst$,$ clk$,$ d$)$

begin

if rst $=\text{'}0\text{'}$ then

q$\_$int;

elsif $($clk$\text{'}$event and clk$=\text{'}1\text{'})$ then

q$\_$int d;

end if;

end process;

q q$\_$int;

end dff;

$------------------------------------------------------$

$($FA$.$vhd$)$ :

entity FA is

port $($x$,$ y$,$ ci: in bit;

s$,$ co: out bit$)$;

end FA;

architecture FA of FA is

begin

s x xor y xor ci;

cox and y$)$ or $($x and ci$)$ or $($y and ci$)$;

end FA;

$-----------------------------------------------------------------------$

$($SA$\_$CC$.$vhd$)$:

library ieee;

use ieee.std$\_$logic$\_1164.$all;

use ieee.std$\_$logic$\_$signed.all;

entity SA$\_$CC is

port$($st$,$ clk: in bit;

sh: out bit$)$;

end SA$\_$CC;

architecture SA$\_$CC of SA$\_$CC is

signal PS$,$ NS: integer range $0$ to $3$;

begin

process $($PS$,$ st$)$

begin

case PS is

when $0=>$if st$=\text{'}1\text{'}$ then

sh;

NS;

else

sh;

NS;

end if;

when $1$ to $2=>$ sh;

NS ps$+1$;

when $3=>$ sh;

NS;

end case;

end process;

process$($clk$)$

begin

if clk'event and clk$=\text{'}1\text{'}$ then

PS NS;

end if;

end process;

end SA$\_$CC;