Question marks, CLO$1]$

Consider the following RISC$-$V Assembly code that is required to be executed on a classical $5-$stage pipelined

processor.

add $15,12,11$

$lw13,4(15)$

$lw12,(2)$

$or13,15,13$

$sw13,(x15)$

a$)$ List down all the hazards that are present in assembly code

b$)$ Assume that pipeline implementation does not have any support for stalling and forwarding to resolve the

hazards. Rewrite the program by inserting the appropriate number of NOP instructions after each hazard for

proper execution. How many cycles will be required to execute this code?

c$)$ Now assume that the hardware implements the forwarding from write back to execute, and memory to

execute stage. How many cycles will now be required to execute this code?