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$124$ FALSE TRUE $2562\mathrm{.}56$

Assume that you have a system that contains a $16-$word cache $(C=16.$ Consider the following RISCV assembly code

addi t$0,$ zero, $4$

addi s$0,$ zero, $0$

loop: beq t$0,$ zero, done

$Iwt1,030(s0)$

$Iwt2,070(s0)$

$Iwt3,054(s0)$

$Iwt3,050(s0)$

addit$0,t0,-1$

$j$ loop

done:

Part$1$: Direct Mapped Cache, b $=1$ word

Fill in the correct size for the cache fields$($Assume $32-$bit memory address size$)$:

$\backslash$table$[[$Tag$,$Set,Byte Offset$],[,,]]$

Place every instruction's data in the correct set in the cache. Also, determine what kind of miss the instruction faces.

$\backslash$table$[[\backslash$table$[[$Instruction$\text{'}$s$],[$data$]],\backslash$table$[[$Set Cache No$.],[$Answer as :$0,3,],[5...]],\backslash$table$[[$Compulsory miss$],[$Answer as: TRUE or$],[$FALSE$]],\backslash$table$[[$Conflict miss $(2$nd$],[$iteration$)],[$Answer as: TRUE or$],[$FALSE$]]],[mem[000.\mathrm{.}030],|,,],[mem[000.\mathrm{.}070],,,],[mem[000.\mathrm{.}054],|,,],[$mem$[0$x$00.\mathrm{.}050],,,]]$

Find the miss rate $($NOTE: if the number is $88\mathrm{.}777778,$ then your answer should be $88\mathrm{.}8)$ :

$($Note: number of misses includes both compulsory and the conflict misses in all iterations$)$

Cache miss rate$=$

$\%$