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QUESTION1 In order to safely enable interrupts again after handling an interrupt, the interrupt mask must be written to in the branch delay slot of the jump returning to the interrupt return address (Sir). O True False QUESTION2 If only a single interrupt device is enabled then, when the interrupt is triggered, the value of the interrupt status register will be the same as the value that was written to the interrupt mask register in order to enable the interrupt. O True QUESTION3 What decimal value needs to be written to the interrupt mask register in order to enable both the timer interrupt and global interrupt bit? NOTE: Only decimal representations will be properly auto-grade. Binary and hexadecimal representations will not be considered correct) QUESTION 4 If you do not know which devices have their interrupt enabled in the mask register. Immediately after an interrupt has been triggered and the ISR is reached, what is the lowest possible value that could be in the interrupt status register.? 0 1 0 2 0 3 None of the above