Questions 1 (30 points): With coincident selection scheme (2D memory), a 128K x 1 memory employs two internal decoders to provide the row select and column select signals. Suppose there are twice as many row-select lines (they are output lines of the row select decoder) than the column-select lines. How many address lines are feeding into the column-select decoder? Questions 2 (35 points): A 64K x 1 memory chip is made of a square memory cell arrays. First part (most significant bits) of an address will feed into the row-select decoder and the remaining address lines will feed into column select decoder. Suppose the address in hexadecimal format is A2BE. Find the physical location (column and row numbers) of the memory cell that is addressed Row Number in Decima: Column Number in Decimal Questions 3 (35 points): A random access read/write memory is constructed of four 1024 word by 4 bit integrated circuits chips with all address, data, and R/W lines tied in parallel (ie: A0 on Chip O to A0 on Chip 1, to A0 on Chip 2, to AO on Chip 3, etc.). The chip selects lines are separately tied to the outputs of a 2-to-4 decoder which has S1 and SO inputs tied to Address bit A11 and A10 respectively as shown below. 1024 4 RANM DATAv ADRS 1024 4 RAN 1024x4 RAM 1024-4 RAM DATA DATA DATA ADRS 10 ADRS ADRS 10 CS cs RW A(9.0) A(11:10) 20-Decoder Fill in the blanks below: The size of RAM is words x bits Questions 1 (30 points): With coincident selection scheme (2D memory), a 128K x 1 memory employs two internal decoders to provide the row select and column select signals. Suppose there are twice as many row-select lines (they are output lines of the row select decoder) than the column-select lines. How many address lines are feeding into the column-select decoder? Questions 2 (35 points): A 64K x 1 memory chip is made of a square memory cell arrays. First part (most significant bits) of an address will feed into the row-select decoder and the remaining address lines will feed into column select decoder. Suppose the address in hexadecimal format is A2BE. Find the physical location (column and row numbers) of the memory cell that is addressed Row Number in Decima: Column Number in Decimal Questions 3 (35 points): A random access read/write memory is constructed of four 1024 word by 4 bit integrated circuits chips with all address, data, and R/W lines tied in parallel (ie: A0 on Chip O to A0 on Chip 1, to A0 on Chip 2, to AO on Chip 3, etc.). The chip selects lines are separately tied to the outputs of a 2-to-4 decoder which has S1 and SO inputs tied to Address bit A11 and A10 respectively as shown below. 1024 4 RANM DATAv ADRS 1024 4 RAN 1024x4 RAM 1024-4 RAM DATA DATA DATA ADRS 10 ADRS ADRS 10 CS cs RW A(9.0) A(11:10) 20-Decoder Fill in the blanks below: The size of RAM is words x bits