Questions related to VHDL Language! will give rating! Thanks in advance!

1- Which of the following aggregations are legal and which one is illegal? ( 30 points) constant CONST: std_logic_vector(3 downto 0) := "1000"; signal s1, s2, ... s5: std_logic_vector(7 downto 0 ); - s1=(7 downto 4 CONST, others ' ); - s2 ' 1 ', 70=> ' 0 ', others => '-' ); - s3