Recording cycle count (number of cycles that have elapsed in time period) is important for calculating the performance of a piece of code. To aid software developers, many processors include an instruction that reads the number of cycles that have elapsed since the processor has reset. In this problem, please explain what architecture components you would add to the MIPS-32 data-path to implement a RDCC instruction. The RDCC (read cycle count) instruction shall copy the number of cycle counts since reset into register 1.

Some hints: * The processor will need to keep track of the number of cycles. * On reset the cycle counter shall be 0. * Every clock cycle the cycle counter shall increment by 1.

Make sure to explain where these components would reside.

After you have designed the architecture, please explain a limitation of this design. How can it be overcome?

Here is the MIPS-32 Single Cycle Architecture:

1 15-0 Sign extend 2 25-21 20-16 PC Instructio Register file Data memory 20-16 n R/W 15-11 0 6x64 decoder Control ROM 1 15-0 Sign extend 2 25-21 20-16 PC Instructio Register file Data memory 20-16 n R/W 15-11 0 6x64 decoder Control ROM