Refer to the following figure, How many JK Flip-Flop are needed to design this state diagram 0/0 00 1/0 1/1 1/0 01 10 0/0 0/0 0/0 11 1/0 1.a o 4.b O 2.co 3.d O ? Which of the following counters has a none zero delay Ripple counter.ao synchronous counters.b .None of the mentioned choices.co .either asynchronous or ripple counter.d the statement that best describes the operation of D flip-flop if the clock is a negative- edge-triggered is The Qoutput is always the same as the Dinput.a O The Qoutput is always the same as the Dinput at the positive edge of the clock.bo The Qoutput is always the same as the clock input if the Dinput equals 1.c O The logic level at the Dinput is transferred to Qon negative edge of the Clock.do To design a BCD Ripple Counter you need at least 3 flip flops", this statement is False .a True.bo ? In the diagram shown in the figure, if you want to update the design to make the counter counts from o up to 31, what should you do QA Count K K Qc > K Logic Add two more JK-flip flops. O Add one more JK-Flip flop.b O Change the type of flip flops to D-Flip flops.co duplicate the number of flip flops.do delete one flip flop.eo