Reg 2. (15%) Give a sequence of instructions and the graphical representation of a 5-stage pipelined datapath with full forwarding and stall mechanism. Assume that when a register is read and written in the same clock cycle, the write is in the 1st half of the clock cycle and the read is in the 2nd half. 1 lw $2,0($1) IF IDEX MEM WB 2 add $3, $2, $1 3 and $4, $3, $2 4 lw $4, 0($2) 5 sw $4, 0($5) (a) List the (true) data dependencies in the code sequence by specifying the instruction pair and the register that causes the dependence; for example, (1.-12, $6). (b) Which of the data dependencies listed in (a) will not cause data hazard in this pipelined datapath? Why? (c) For those data dependencies that may cause data hazards, which of the data hazards may be resolved by applying forwarding only? Why? (d) For those data dependencies that may cause data hazards, which of the data hazards should be resolved by applying both stall and forwarding? Why? (e) How many cycles are required to complete the code sequence in this pipeline? Why