Reorder the above code to reduce the stalls without changing the functionality. Assume there is forwarding, no branch prediction, and no duplicate copies of instruction memory or data memory.

Loop:

LSL X9, X20, #3

ADD X9, X9, X22

LDUR X9, [X9, #0]

ADD X9, X9, X21

LSL X10, X19, #3

ADD X10, X10, X22

STUR X9, [X10, #0]

LSL X9, X21, #3

ADD X9, X9, X22

LDUR X9, [X9, #0]

SUB X19, X20, X9

CBNZ X19, Loop

ADDI X19, XZR, #32