Select the best Alternative/S: (5 pts ea, except #9) Total: 50pts 1. Which one of the following features of VHDL, supports BEST the creation of large and complex but understandable models. a. Composing a model in terms of other simpler model instances b. Allowing the creation of arbitrarily large and complex single models C. Supporting fundamental and universal AND/OR/NOT Boolean function d. Allowing the creation of Behavioral, Equation or Structural single model architectures e. Abstracting the interface of a model from multiple architectural implementations 2. The RS-232 Standard uses a serial transmission/reception protocol that (choose all that apply): a. Serially transmits one byte at a time with an unspecified maximum delay between bytes b. Frames each data byte with two start bits and one stop bit C. The least significant bit is the last serial data bit transmitted. d. The serial data between devices requires a Ground, a Txd, a Rxd and a Clock signal e. Originally it was defined for communication between a digital device and a modem 3. The control/status signals of the classical 74163 Counter are the following (mark all that apply): a. Parallel load data-inputs and count-outputs (4 bits each ) b. Load Enable C. Carry-in and Carry-out d. Count Enable e. Reset 4. The set of operations or functions usually implemented by a Universal Shift Register when it's clock transitions are: a. Hold current register value (even if the clock transitions) b. Shift Right C. Complement register value d. Shift Left e. Parallel Load 5. For a correctly designed state transition diagram the following properties must be true a. All outputs must dependent or be a function of the state, or of the state and the inpu b. The set of all branching conditions from a particular state must cover all the min-term combinations of the input variables c. Only one of the branches from the current state can be active at the same time