Show your work for the following for full credit.$($a$)$ What is the clock cycle time in a pipelined and non$-$pipelined processor?WB$200$psSTUR$15\%2($b$)$ What is the total latency of an LDUR instruction in a pipelined and non$-$pipelined processor?$($c$)$ If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original st: which stage would you split and what is the new clock cycle time of the processor?