So I have the truth table done along with everything else but I need help writing the Verilog code.

What I have is:

module HW8P1 (A1, A0, B1, B0, O);

input A1,A0,B1,B0;

output O;

assign O = (~A1 & ~A0 & ~B1 & B0) | (~A1 & ~A0 & B1 & B0) | (~A1 & ~A2 & B1 & ~B0) | (~A1 & A0 & B1 & B0) | (~A1 & A0 & B1 & ~B0) | (A1 & ~A0 & B1 & B0)

endmodule

When I run it it says I have a syntax error on line 8 which is the endmodule and then another syntax error in the continuous assignment; the assign O line.

Design a comparator that takes four bits (Al, A0, B1, B0) as input and produces one bit (O) as output. O is 1 if and only if the binary value of AlA0 is less than the B1B0 when both pairs of bits are regarded as 2-bit unsigned integers (a) Complete the following truth table. (10 points) Inputs Output 0 0 0 0 0 0 0 0 0 (b) Write the sum-of-product form for the output O without any simplification. (10 points)